Delta-sigma analog-to-digital converters promise high resolution without the stringent requirements on analog device matching of conventional analog data converters. Delta-sigma data converters are a good match to VLSI MOS technologies which can support extensive digital signal processing.
However, delta sigma techniques put heavy burdens on digital post processing of the signal. First, the decimation filter needs to decimate the high sample rate and coarsely quantized signal to high resolution Nyquist sampling rate data. Second, the decimation filter needs to provide sufficient attenuation of unwanted high frequency signals such that they will have minimum aliasing to the base band after decimation.
Two approaches are widely used in implementing the decimation filter. The first approach uses a one stage FIR (Finite Impulse Response) filter. Hardware complexity usually limits this approach to 64 OSR (oversampling ratio) or lower. Also, a one stage FIR filter has relatively low quantization noise filtering capability.
There are several reasons to use a delta sigma modulator with an OSR greater than 64. The noise in a delta-sigma analog-to-digital converter is mainly dominated by thermal noise sampled on to the input capacitors. The inband noise power is given by ##EQU1## so with the increase of OSR we can either improve the performance of the analog-to-digital converters or reduce the capacitor sizes while maintaining the same performance. With higher OSR, we can also reduce the order of the modulators, thus improve the stability and reducing the analog modulator area. For example, to achieve 16-bit performance at 64 OSR, a fourth order modulator is needed, but with 128 OSR a third order modulator will suffice.
As a second approach, multi-stage decimation filter is popular for higher OSR. The multi-stage decimation filter usually consists of several cascaded comb filters and a two stage FIR filter. The comb filters decimate the signal to 4 Fs, where Fs is Nyquist frequency or base band sampling frequency, and each FIR filter decimates the sample rate by a factor of two. There are two drawbacks with this approach. First, a large data storage unit (RAM) is needed. Second, complicated addressing circuitry is needed to compute the two stage FIR filter.
In delta-sigma analog-to-digital data converters, the analog modulator contributes unwanted DC offset. In some cases, a DC offset is deliberatively added to the input of the analog modulator to move the tones inherently associated with delta sigma modulation such that when decimated, these undesirable tones will not alias to the audible frequency band. A common way to cancel the DC offset is offset calibration during the initial power up of the chip. This kind of offset calibration scheme sometimes is not satisfactory because the DC offset drifts due to temperature change or switching at the input source.
It therefore can be appreciated that a decimation filter which can decimate a 128 OSR in a relatively small amount of chip area, and which effectively attenuates unwanted DC offset is highly desirable.